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NB4L52 2.5V/3.3V/5V Differential Data/Clock D Flip-Flop with Reset
Multi-Level Inputs to LVPECL Translator w/ Internal Termination
The NB4L52 is a differential Data and Clock D flip-flop with a differential asynchronous Reset. The differential inputs incorporate internal 50 W termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3x3 mm 16 pin QFN package.
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MARKING DIAGRAM*
16 1
1 QFN-16 MN SUFFIX CASE 485G A L Y W
NB4L 52 ALYW
* * * * * * * *
Maximum Input Clock Frequency > 4 GHz Typical 330 ps Typical Propagation Delay 145 ps Typical Rise and Fall Times Differential LVPECL Outputs, 750 mV Peak-to-Peak, Typical Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V Internal Input Termination Resistors, 50 W Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices -40C to +85C Ambient Operating Temperature
= Assembly Location = Wafer Lot = Year = Work Week
*For additional marking information, refer to Application Note AND8002/D.
VTD D Db VTDb VTCLK CLK CLKb VTCLKb Clock Reset Qb Data Q
VTR R Rb VTRb
Figure 1. Logic Diagram
Table 1. TRUTH TABLE
R H L L *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. D x L H CLK x Z Z Q L L H
Z = LOW to HIGH Transition x = Don't Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2005
1
December, 2005 - Rev. 0
Publication Order Number: NB4L52/D
NB4L52
VTR 16 R 15 R 14 VTR 13 12 11 NB4L52 D VTD 3 4 5 6 7 8 10 9 Q VEE
VTD D
1 2
VCC Q
VTCLK CLK
CLK VTCLK Exposed Pad (EP)
Figure 2. Pinout: QFN-16 (Top View)
Table 2. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - Name VTD D D VTD VTCLK CLK CLK VTCLK VEE Q Q VCC VTR R R VTR EP I/O - ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - ECL Output ECL Output - - LVECL, LVCMOS, LVTTL Input LVECL, LVCMOS, LVTTL Input - - Description Internal 50 W Termination Pin. (See Table 4) Noninverted Differential Input. (Note 1) Inverted Differential Input. (Note 1) Internal 50 W Termination Pin. (See Table 4) Internal 50 W Termination Pin. (See Table 4) Noninverted Differential Input. (Note 1) Inverted Differential Input. (Note 1) Internal 50 W Termination Pin. (See Table 4) Negative Supply Voltage Inverted Differential Output. Typically terminated with 50 W resistor to VCC - 2.0 V. Noninverted Differential Output. Typically terminated with 50 W resistor to VCC - 2.0 V. Positive Supply Voltage Internal 50 W Termination Pin. (See Table 4) Noninverted Differential Reset Input. (Note 1) Inverted Differential Reset Input. (Note 1) Internal 50 W Termination Pin. (See Table 4) The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pin (VTD, VTDB, VTR, VTRB, VTCLK, VTCLKB) are connected to a common termination voltage or left open, and if no signal is applied on D/DB,CLK/CLKB,R/RB input then the device will be susceptible to self-oscillation.
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Table 3. ATTRIBUTES
Characteristics ESD Protection Machine Model Charged Device Model Moisture Sensitivity (Note 2) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Oxygen Index: 28 to 34 Level 1 UL 94 V-0 @ 0.125 in 164 Human Body Model Value > 2 kV > 200 V > 1 kV
Table 4. MAXIMUM RATINGS
Symbol VCC VEE VI VINPP IIN Iout TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |D - D| Static Surge Continuous Surge Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 LFPM 500 LFPM 2S2P (Note 4) < 3 sec @ 260C 16 QFN 16 QFN 16 QFN Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VI v VCC VI w VEE Condition 2 Rating 6.0 -6.0 6.0 -6.0 2.8 45 80 25 50 -40 to +85 -65 to +150 41.6 35.2 4.0 265 Unit V V V V V mA mA mA mA C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 3. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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Table 5. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS
(VCC = 2.375 V to 5.5 V, VEE = 0 V, TA = -40C to +85C) Symbol IEE VOH Characteristic Power Supply Current (Inputs and Outputs Open) Output HIGH Voltage (Note 5, 6) VCC = 5.0 V VCC = 3.3 V VCC = 2.5 V VOL Output LOW Voltage (Note 5, 6) VCC = 5.0V VCC = 3.3V VCC = 2.5V DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 6 & 8) Vth VIH VIL Input Threshold Reference Voltage Range (Note 7) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage 1050 Vth + 150 VEE VCC - 150 VCC Vth - 150 mV mV mV VCC - 1145 3855 2155 1355 VCC - 1945 3055 1355 555 Min Typ 16 VCC - 1020 3980 2280 1480 VCC - 1770 3230 1530 730 Max 25 VCC - 895 4105 2405 1605 VCC - 1600 3400 1700 900 Unit mA mV
mV
DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 7 & 9) VIHD VILD VCMR VID IIH IIL RTIN Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration) (Note 8) Differential Input Voltage (VIHD - VILD) Input HIGH Current Input LOW Current D / Db, CLK / CLKb, R /Rb D / Db, CLK / CLKb, R /Rb (VTx/VTxb Open) (VTx/VTxb Open) 1200 VEE 1125 150 -150 -150 40 50 VCC VCC - 150 VCC - 75 2800 150 150 60 mV mV mV mV mA mA W
Internal Input Termination Resistor
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. LVPECL outputs loaded with 50 W to VCC - 2.0 V for proper operation. 6. Input and output parameters vary 1:1 with VCC. 7. Vth is applied to the complementary input when operating in single-ended mode. 8. VCMRMIN varies 1:1 with VEE, VCMRMAX varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal.
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Table 6. AC CHARACTERISTICS VCC = 2.375 V to 5.5 V; VEE = 0 V (Note 9)
-40C Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPPmin) (Note 11) (See Figure 4) fin v 2.0 GHz fin v 3.0 GHz fin v 4.0 GHz Propagation Delay to Output Differential Setup Time Hold Time Reset Recovery Minimum Pulse Width R/R CLK to Q R to Q 100 50 400 250 100 50 400 250 1 1 1 20 20 20 150 80 135 2800 190 150 80 145 2800 190 150 80 155 2800 190 mV ps Min 530 490 380 Typ 770 720 580 Max Min 530 490 380 25C Typ 780 730 580 330 400 500 100 50 400 250 Max Min 530 490 380 85C Typ 760 680 530 ps ps ps ps ps ps Max Unit mV
tPLH, tPHL ts th tRR tPW tJITTER
RMS Random Clock Jitter (Note 10) fin v 2.0 GHz fin v 3.0 GHz fin v 4.0 GHz Peak-to-Peak Data Dependent Jitter fin v 2.0 GHz fin v 3.0 GHz fin v 4.0 GHz Input Voltage Swing/Sensitivity (Differential Configuration) (Note 11) Output Rise/Fall Times @ 0.5 GHz (20% - 80%)
VINPP tr tf
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured by forcing VINPPt (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%). 10. Additive RMS jitter with 50% duty cycle clock signal at 2 GHz & 3 GHz. 11. Input and output voltage swing is a single-ended measurement operating in differential mode.
CLK VIH Vth VIL CLK
CLK CLK Vth
Figure 3. Differential Input Driven Single-Ended
Figure 4. Differential Inputs Driven Differentially
CLK CLK
VID = |VIHD(CLK) - VILD(CLK)| VIHD VILD
Figure 5. Differential Inputs Driven Differentially
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VCC Vthmax CLK Vth VIHmin CLK VILmin VIHmax VILmax VCMR VCC VCMmax VIHDmax VILDmax
Vthmin VEE
VCMmin VEE
VIHDmin VILDmin
Figure 6. Vth Diagram
Figure 7. VCMR Diagram
VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL)
800 700 600 500 400 300 200 100 0 0 1 2 3 4 fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 8. Output Voltage Amplitude (VOUTPP) versus Clock Output Frequency at Ambient Temperature (Typical) (fout QA/QB) = fin B n; fin v 3.0 GHz).
CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 9. AC Reference Measurement
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NB4L52
NB6L239 Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 10. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device NB4L52MNG NB4L52MNR2G Package QFN-16, 3 x 3 mm (Pb-Free) QFN-16, 3 x 3 mm (Pb-Free) Shipping 123 Units / Rail 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPS I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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NB4L52
PACKAGE DIMENSIONS
16 PIN QFN CASE 485G-01 ISSUE B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50
D
A B
PIN 1 LOCATION
0.15 C 0.15 C 0.10 C TOP VIEW
16 X
0.08 C SIDE VIEW A1 C
16X
L
5
NOTE 5 4
16X
K
1 12
16X
0.10 C A B 0.05 C
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CCC CCC CCC
(A3) D2 e
8 9 16 13
E
A
SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
EXPOSED PAD
E2 e
b BOTTOM VIEW
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NB4L52/D

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